Integrated circuits (ICs) are easily damaged by excess voltages, and the common sources of these potentially damaging voltages include electrostatic discharge (ESD). ESD is a transfer of electrostatic charge between bodies or surfaces at different electrostatic potentials either through direct contact or through an induced electrical field.
ICs built using semiconductors, such as silicon and insulating materials such as silicon dioxide, may be permanently damaged when subjected to high voltages during ESD events. Conventionally, on-chip circuits protect ICs during ESD events. One conventional protection circuits is a shallow trench isolation (STI) diode.
FIG. 1 is a cross-sectional view illustrating a conventional shallow trench isolation (STI) diode. An STI diode 100 includes a substrate 102 having a first doped region 106 (e.g., an N-type region) and a second doped region 108 (e.g., a P-type region). A shallow trench isolation (STI) region 104 separates the first doped region 106 and the second doped region 108. Shallow trench isolation regions 104 are also provided on the periphery of the diode 100. A silicide layer including a silicided portion 116 is formed on the first doped region 106 and a second silicided portion 118 is formed on the second doped region 108. A conduction path 120 for carriers from the first doped region 106 to the second doped region 108 produced by carrier injection extends around the STI region 104 located between the doped regions 106, 108. STI diodes have a long current conduction path 120, which results in a slow turn-on time and a high turn-on resistance.
In certain circuits, such as a low noise amplifier, a high speed diode protects the IC, and especially an input gate, from voltage build up (e.g., overshoot) due to delay in conduction. A gated diode offers faster turn-on time than that of the STI diode by reducing the length of the conduction path.
FIG. 2 is a cross-sectional view illustrating a conventional gated diode. A gated diode 200 includes a substrate 202 having a first doped region 206 (e.g., a P-type region) and a second doped region 208 (e.g., an N-type region). Shallow trench isolation (STI) regions 204 are located on the periphery of the diode 200, but not between the doped regions 206, 208. Between the first doped region 206 and the second doped region 208 and on a surface of the substrate 202 a gate includes a gate oxide layer 220, a gate electrode 222, and spacers 224. A first lightly doped region 212 (e.g., a lightly doped drain (LDD) implant) and a second lightly doped region 214 are located between the first doped region 206 and the second doped region 208 and abutted against the first doped region 206 and the second doped region 208, respectively. A salicide layer including a salicide portion 216 is formed on the first doped region 206 and a second salicide portion 218 is formed on the second doped region 208. Likewise, a silicide portion 226 is formed on the gate electrode 222. A conduction path 240 between the doped regions 206, 208 is shorter in the gated diode 200 than the conduction path 120 of the STI diode 100.
The thin gate oxide 220 of the gated diode 200 is susceptible to oxide rupture from over voltages during, for example, ESD events. As ICs are manufactured at smaller sizes, the thickness of the gate oxide 220 decreases and the gated diode 200 becomes more susceptible to oxide rupture. Additionally, the gated diode 200 has a low reverse breakdown voltage and increased capacitance. The increased capacitance in comparison to the STI diode 100 results from intrinsic capacitance between the gate and the doped regions. For example, additional capacitance results from the gate electrode 222 to the first lightly doped region 212 and from the gate electrode 222 to the second lightly doped region 214.
Thus, there is a need for a diode with low turn-on time, low capacitance, low turn-on resistance, reliable operation, and good clamping characteristics.